[Splave]

I Really like this board

http://valid.canardpc.com/show_oc.php?id=1189116
Water (not pushing past 1.45 on water)

Target CPU Frequency        4883MHz
Target DRAM Frequency        1576MHz

LN2 Mode:            Disabled***
QPI Loadline Calibration:    Enabled***

Sync Mode            [Enabled]
AI Overclock Tuner        [Manual]
OC From CPU level Up        [Auto]
CPU Ratio Setting        [31.0]
CPU Turbo Power Limit        [Disabled]

>CPU Configuration----------------------------
CPU Ratio Setting        [31.0]
C1E Support            [Disabled]
Hardware Prefetcher        [Enabled]
Adjacent Cache Line Prefetcher    [Enabled]
Intel(R) Virtualiyation Tech    [Disabled]
CPU TM Function            [Disabled]
Execute Disable Bit        [Disabled]
Intel(R) HT Technology        [Disabled]
Active Processor Cores        [All]
A20M                [Disabled]
Intel(R) SpeedStep(TM) Tech    [Disabled]
Intel(R) C-STATE Tech        [Disabled]
C State package limit setting    [Auto]
----------------------------------------------

BCLK Frequency            [158]
PCIE Frequency            [100]
DRAM Frequency            [1576]
UCLK Frequency            [3258]
QPI Link Data Rate        [4.8mt/s]

Memory Configuration Protect    [enabled]

>DRAM Timing Control--------------------------
CAS# Latency              6    [8]
RAS# to CAS# Delay          7    [8]
RAS# PRE Time              6    [8]
RAS# ACT Time             18    [24]
RAS# to RAS# Delay          4    [auto]
REF Cycle Time             72    [88]
WRITE Recovery Time         12    [auto]
READ to PRE Time          6    [auto]
FOUR ACT WIN Time         24    [Auto]
Back-To-BackCAS# Delay          0    [Auto]

Timing Mode             1N    [1N]
Round Trip Latency on CHA    60    [auto]
Round Trip Latency on CHB    62    [auto]
Round Trip Latency on CHC    64    [auto]

WRITE To READ Delay(DD)          8    [Auto]
WRITE To READ Delay(DR)          8    [Auto]
WRITE To READ Delay(SR)         18    [Auto]
READ To WRITE Delay(DD)          7    [Auto]
READ To WRITE Delay(DR)          7    [Auto]
READ To WRITE Delay(SR)          7    [Auto]
READ To READ Delay(DD)          7    [Auto]
READ To READ Delay(DR)          6    [Auto]
READ To READ Delay(SR)          4    [Auto]
WRITE To WRITE Delay(DD)      8    [Auto]
WRITE To WRITE Delay(DR)      8    [Auto]
WRITE To WRITE Delay(SR)     18    [Auto]
----------------------------------------------

CPU Differential Amplitude    [1000]
CPU Clock Skew            [Auto]
IOH Clock Skew            [Auto]
------------ Extreme Engine Digi+ ------------
Digi+ PWR Mode            [T-Balanced]
PWR Volt. Control        [7v]
Load-Line Calibration        [50%]
CPU Voltege OCP            [Disabled]
CPU PWM Frequency        [800kHz]

Extreme OV            [Disabled]
Extreme OC            [Auto]

CPU Voltage        1.415    [1.442]
CPU PLL Voltage     1.812    [1.808]
QPI/DRAM Core Voltage    1.310    [1.400]
DRAM Bus Voltage    1.654    [1.683]

>DRAM REF Voltages----------------------------
DRAM DATA REF Voltage on CHA    [Auto]
DRAM CTRL REF Voltage on CHA    [Auto]
DRAM DATA REF Voltage on CHB    [Auto]
DRAM CTRL REF Voltage on CHB    [Auto]
DRAM DATA REF Voltage on CHC    [Auto]
DRAM CTRL REF Voltage on CHC    [Auto]
----------------------------------------------

IOH Voltage        1.244    [1.202]
IOH PCIE Voltage    1.508    [auto]

ICH Voltage        1.111    [1.202]
ICH PCIE Voltage        [Auto]

---------- Spread Spectrum Control -----------
CPU Spread Spectrum        [Disabled]
DRAM Spread Spectrum        [Disabled]

***on-board jumper dependant

Full LLC cause a bit of overvolt for me, 50% seems good. PWR volt control over 8v not necessary on water. Will try some higher bclk stuff and report back.