Overclockaholics Forums - DDR3 Subtimings / Timing Control

Prelude

uncore multi(980x) - 1.5x of ram
*1.5x only for 980x
**eva formula to be added later

vtt set to 1.4v ..uncore can go as high as 4.2ghz

DRAM Timing Control

CAS Latency(tCL) 6/7/8 depends from memory chipsips..psc/hyper/sams
RAS to CAS Delay(tRCD) 6/7/8 depends on memory
RAS - PRE Time(tRP) 4/5/6/7/8 can be equal to..or less than tCL ......4 and 5 are veryyyy tight

RAS - ACT Time(tRAS) .tRAS(minimum)=tCL + tRCD + 2.
**frm tweakers.fr & frm mushkin..
***tRAS is also sum of first 3 subtimings(wiki)... tRAS=tCL + tRCD +tRP

tRAS = 15-17 tight

RAS to RAS Delay(tRRD) default/stock = 7, the lower the better 6 , 5, 4(gtr) , 3 2 1 doable with hypers

REF Cycle Time(tRFC) - higher for tripple channel. (50-1xx) Auto? 53 doabled
WRITE Recovery Time(tWR) 12//13/14/15/16 .....formula:tWR=tRAS-tRCD = 24-8 =16, 21-7 = 14, 18-6 =12, 11 doabled
WRITE to PreCharge Time(tWTP) 21(minimum-very tight)-29(for high clocks )......formula:

Write to Read Delay (tWTR) usually: 2 - 8

READ to PRE Time(tRTP) 6/7/8/9
FOUR ACT WIN Time - 35/36/37/38/39/40/41/42/43/44/45 ....1 is doabled
Back-To-BackCAS Delay must be disabled or set to zero.

tRC= tRAS + tRP
tRC from xp is around 43-45

Timing Mode - auto sets this to around 60+, typically (63.65.66)...some do @ 55,56..57
Round Trip Latency on CHA
Round Trip Latency on CHB must be RTL_CHA +1 or +2
Round Trip Latency on CHC must be RTL_CHB +1 or +2,

RTL = xxx need to convert formula from RAJA

WRITE To READ Delay(DD) auto
WRITE To READ Delay(DR) auto
WRITE To READ Delay(SR) auto
READ To WRITE Delay(DD) auto
READ To WRITE Delay(DR) auto
READ To WRITE Delay(SR) auto
READ To READ Delay(DD) auto
READ To READ Delay(DR) auto
READ To READ Delay(SR) auto
WRITE To WRITE Delay(DD) auto
WRITE To WRITE Delay(DR) auto
WRITE To WRITE Delay(SR) auto

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QPI/DRAM Core Voltage -- same as vtt - intel specs (980x 1.4vmax)....
DRAM Bus Voltage -- must not be more than 0.5v of vtt - use 1.66v not 1.64v...i prefer 1.7xv

>DRAM REF Voltages - higher might help...must be the same.
DRAM DATA REF Voltage on CHA 0.75v
DRAM CTRL REF Voltage on CHA 0.75v
DRAM DATA REF Voltage on CHB 0.75v
DRAM CTRL REF Voltage on CHB 0.75v
DRAM DATA REF Voltage on CHC 0.75v
DRAM CTRL REF Voltage on CHC 0.75v

newstuff

Quote:

*Tested on EVGA P55 FTW & EVGA P55 FTW 200 main-boards with Intel Core i7 CPU
*When setting up your EVO TWO 2500MHz C9 Dual Channel Kit on the EVGA P55 FTW and P55 FTW 200 Motherboards, please do the following: Please go to Frequency/Voltage Control and leave the DIMM Voltage as [AUTO] then select Memory Configuration to set DRAM tRFC from 80 (default) to 110.

****this is not final.
*****suggestions/tips?
******colors? :D

********************red = near limit....